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note: this is a summary document. the complete document is available on the atmel website at www.atmel.com. features ? incorporates the arm7tdmi ? arm ? thumb ? processor ? high-performance 32-bit risc architecture ? high-density 16-bit instruction set ? leader in mips/watt ? embeddedice ? in-circuit emulation, debug communication channel support internal high -speed flash ? 512 kbytes (AT91SAM7XC512) organized in two banks of 1024 pages of 256 bytes (dual plane) ? 256 kbytes (at91sam7xc256) organized in 1024 pages of 256 bytes (single plane) ? 128 kbytes (at91sam7xc128) organized in 512 pages of 256 bytes (single plane) ? single cycle access at up to 30 mhz in worst case conditions ? prefetch buffer optimizing thumb instruction execution at maximum speed ? page programming time: 6 ms, including page auto-erase, full erase time: 15 ms ? 10,000 write cycles, 10-year data retention capability, sector lock capabilities, flash security bit ? fast flash programming interface for high volume production internal high-speed sram, single-cycle access at maximum speed ? 128 kbytes (AT91SAM7XC512) ? 64 kbytes (at91sam7xc256) ? 32 kbytes (at91sam7xc128) memory controller (mc) ? embedded flash controller, abort status and misalignment detection reset controller (rstc) ? based on power-on reset cells and low-power factory-calibrated brownout detector ? provides external reset signal shaping and reset source status clock generator (ckgr) ? low-power rc oscillator, 3 to 20 mhz on-chip oscillator and one pll power management controller (pmc) ? power optimization capab ilities, including sl ow clock mode (down to 500 hz) and idle mode ? four programmable external clock signals advanced interrupt controller (aic) ? individually maskable, eight-level priority, vectored interrupt sources ? two external interrupt sources and one fa st interrupt source, spurious interrupt protected debug unit (dbgu) ? 2-wire uart and support for debug communication channel interrupt, programmable ice access prevention periodic interval timer (pit) ? 20-bit programmable counter pl us 12-bit interval counter windowed watchdog (wdt) ? 12-bit key-protected programmable counter ? provides reset or interrupt signals to the system ? counter may be stopped while the processor is in debug state or in idle mode real-time timer (rtt) ? 32-bit free-running counter with alarm ? runs off the internal rc oscillator at91 arm thumb-based microcontrollers AT91SAM7XC512 at91sam7xc256 at91sam7xc128 summary preliminary 6209bs?atarm?03-sep-06
2 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary two parallel input/output controllers (pio) ? sixty-two programmable i/o lines multiplexed with up to two peripheral i/os ? input change interrupt ca pability on each i/o line ? individually programmable open-drain, pull-up resistor and synchronous output seventeen peripheral dma controller (pdc) channels one advanced encryption system (aes) ? 256-, 192-, 128-bit key algorithm, compliant with fips pub 197 specifi cations (AT91SAM7XC512) ? 128-bit key algorithm, compliant with fips pub 197 specifications (at91sam7xc256/128) ? buffer encryption/decryption capabilities with pdc one triple data encryption system (tdes) ? two-key or three-key algorithms, co mpliant with fips pub 46-3 specifications ? optimized for triple data encryption capability one usb 2.0 full speed (12 mb its per second) device port ? on-chip transceiver, 1352-byte configurable integrated fifos one ethernet mac 10/100 base-t ? media independent interface (mii) or re duced media independ ent interface (rmii) ? integrated 28-byte fifos and dedicated dma channels for transmit and receive one part 2.0a and part 2.0b compliant can controller ? eight fully-programmable message object mailboxes, 16-bit time stamp counter one synchronous serial controller (ssc) ? independent clock and frame sync sign als for each receiver and transmitter ? i2s analog interface support, time division multiplex support ? high-speed continuous data stream ca pabilities with 32-bit data transfer two universal synchronous/asynchrono us receiver transmitters (usart) ? individual baud rate generator, ir da infrared modulation/demodulation ? support for iso7816 t0/t1 smart card, hardware handshaking, rs485 support ? full modem line support on usart1 two master/slave serial peripheral interfaces (spi) ? 8- to 16-bit programmable da ta length, four external peripheral chip selects one three-channel 16-bi t timer/counter (tc) ? three external clock inputs, two multi-purpose i/o pins per channel ? double pwm generation, capture/waveform mode, up/down capability one four-channel 16-bit power width modulation controller (pwmc) one two-wire interface (twi) ? master mode support only, all two-wire atmel ? eeproms supported one 8-channel 10-bit analog-to-digital converter, four channels multiplexed with digital i/os sam-ba ? boot assistant ? default boot program ? interface with sam-ba gr aphic user interface ieee 1149.1 jtag boundary scan on all digital pins 5v-tolerant i/os, including four high-current drive i/o lines, up to 16 ma each power supplies ? embedded 1.8v regulator, drawing up to 10 0 ma for the core and external components ? 3.3v vddio i/o lines power supply, independent 3.3v vddflash flash power supply ? 1.8v vddcore core power supply with brownout detector fully static operation: up to 55 mhz at 1.65v and 85 " c worst case conditions available in 100-lead lqfp green and 100-ball tfbga green packages
3 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 1. description atmel's AT91SAM7XC512/256/128 is a member of a series of highly integrated flash microcon- trollers based on the 32-bit arm risc processor. it features 512/256/128 kbyte high-speed flash and 128/64/32 kbyte sram, a large set of peripherals, including an 802.3 ethernet mac, a can controller, an aes 128 encryption accelerator and a triple data encryption system. a complete set of system functions minimizes the number of external components. the embedded flash memory can be programmed in-system via the jtag-ice interface or via a parallel interface on a production programmer pr ior to mounting. built-in lock bits and a secu- rity bit protect the firmware from accidental overwrite and preserve its confidentiality. the AT91SAM7XC512/256/128 system controller includes a reset controller capable of manag- ing the power-on sequence of the microcontroller and the complete system. correct device operation can be monitored by a built-in brownout detector and a watchdog running off an inte- grated rc oscillator. by combining the arm7tdmi processor with on-chip flash and sram, and a wide range of peripheral functions, includin g usart, spi, can controller, et hernet mac, aes 128 accelera- tor, tdes, timer counter, rtt and analog-to-di gital converters on a monolithic chip, the AT91SAM7XC512/256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring secure communication over, for example, ethernet, can wired and zigbee ? wireless networks. 1.1 configuration summary of the AT91SAM7XC512/256/128 the AT91SAM7XC512, at91sam7xc2 56 and at91sam7xc128 differ only in memory sizes. table 1-1 summarizes the configurations of the two devices. table 1-1. configuration summary device flash flash organization sram aes tdes AT91SAM7XC512 512k bytes dual plane 128k bytes 1 aes 256/192/128 1 at91sam7xc256 256k bytes single plane 64k bytes 1 aes 128 1 at91sam7xc128 128k bytes single plane 32k bytes 1 aes 128 1
4 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 2. AT91SAM7XC512/256/128 block diagram figure 2-1. AT91SAM7XC512/256/128 block diagram tdi tdo tms tck nrst fiq irq0-irq1 pck0-pck3 pmc peripheral bridge peripheral dma controller aic pll rcosc sram 128/64/32 kbytes arm7tdmi processor ice jtag scan jtagsel pioa usart0 ssc timer counter rxd0 txd0 sck0 rts0 cts0 spi0_npcs0 spi0_npcs1 spi0_npcs2 spi0_npcs3 spi0_miso spi0_mosi spi0_spck flash 512/256/128 kbytes reset controller drxd dtxd tf tk td rd rk rf tclk0 tclk1 tclk2 tioa0 tiob0 tioa1 tiob1 tioa2 tiob2 memory controller abort status address decoder misalignment detection pio pio apb por embedded flash controller ad0 ad1 ad2 ad3 adtrg pllrc 17 channels pdc pdc usart1 rxd1 txd1 sck1 rts1 cts1 dcd1 dsr1 dtr1 ri1 pdc pdc pdc pdc spi0 pdc adc advref pdc pdc tc0 tc1 tc2 twd twck twi osc xin xout vddin pwmc pwm0 pwm1 pwm2 pwm3 1.8 v voltage regulator usb device fifo ddm ddp transceiver gnd vddout bod vddcore vddcore vddflash ad4 ad5 ad6 ad7 vddflash fast flash programming interface erase pio pgmd0-pgmd15 pgmncmd pgmen0-pgmen1 pgmrdy pgmnvalid pgmnoe pgmck pgmm0-pgmm3 vddio tst dbgu pdc pdc pit wdt rtt system controller vddcore can canrx cantx pio ethernet mac 10/100 etxck-erxck-erefck etxen-etxer ecrs-ecol, ecrsdv erxer-erxdv erx0-erx3 etx0-etx3 emdc emdio dma fifo piob spi1_npcs0 spi1_npcs1 spi1_npcs2 spi1_npcs3 spi1_miso spi1_mosi spi1_spck pdc pdc spi1 aes 128 pdc pdc ef100 sam-ba tdes pdc pdc rom vddflash
5 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 3. signal description table 3-1. signal description list signal name function type active level comments power vddin voltage regulator and adc power supply input power 3v to 3.6v vddout voltage regulator output power 1.85v vddflash flash and usb power supply power 3v to 3.6v vddio i/o lines power supply power 3v to 3.6v vddcore core power supply power 1.65v to 1.95v vddpll pll power 1.65v to 1.95v gnd ground ground clocks, oscillators and plls xin main oscillator input input xout main oscillator output output pllrc pll filter input pck0 - pck3 programmable clock output output ice and jtag tck test clock input no pull-up resistor tdi test data in input no pull-up resistor. tdo test data out output tms test mode select input no pull-up resistor. jtagsel jtag selection input pull-down resistor. flash memory erase flash and nvm configuration bits erase command input high pull-down resistor reset/test nrst microcontroller reset i/o low pull-up resistor, open drain output tst test mode select input high pull-down resistor debug unit drxd debug receive data input dtxd debug transmit data output aic irq0 - irq1 external interrupt inputs input fiq fast interrupt input input pio pa0 - pa30 parallel io controller a i/o pulled-up input at reset pb0 - pb30 parallel io controller b i/o pulled-up input at reset
6 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary usb device port ddm usb device port data - analog ddp usb device port data + analog usart sck0 - sck1 serial clock i/o txd0 - txd1 transmit data i/o rxd0 - rxd1 receive data input rts0 - rts1 request to send output cts0 - cts1 clear to send input dcd1 data carrier detect input dtr1 data terminal ready output dsr1 data set ready input ri1 ring indicator input synchronous serial controller td transmit data output rd receive data input tk transmit clock i/o rk receive clock i/o tf transmit frame sync i/o rf receive frame sync i/o timer/counter tclk0 - tclk2 external clock inputs input tioa0 - tioa2 i/o line a i/o tiob0 - tiob2 i/o line b i/o pwm controller pwm0 - pwm3 pwm channels output serial peripheral interface - spix spix_miso master in slave out i/o spix_mosi master out slave in i/o spix_spck spi serial clock i/o spix_npcs0 spi peripheral chip select 0 i/o low spix_npcs1-npcs3 spi peripheral chip select 1 to 3 output low two-wire interface twd two-wire serial data i/o twck two-wire serial clock i/o table 3-1. signal description list (continued) signal name function type active level comments
7 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary analog-to-digital converter ad0-ad3 analog inputs analog digital pulled-up inputs at reset ad4-ad7 analog inputs analog analog inputs adtrg adc trigger input advref adc reference analog fast flash programming interface pgmen0-pgmen1 programming enabling input pgmm0-pgmm3 programming mode input pgmd0-pgmd15 programming data i/o pgmrdy programming ready output high pgmnvalid data direction output low pgmnoe programming read input low pgmck programming clock input pgmncmd programming command input low can controller canrx can input input cantx can output output ethernet mac 10/100 erefck reference clock input rmii only etxck transmit clock input mii only erxck receive clock input mii only etxen transmit enable output etx0 - etx3 transmit data outp ut etx0 - etx1 only in rmii etxer transmit coding error output mii only erxdv receive data valid input mii only ecrsdv carrier sense and data valid input rmii only erx0 - erx3 receive data input erx0 - erx1 only in rmii erxer receive error input ecrs carrier sense input mii only ecol collision detected input mii only emdc management data clock output emdio management data input/output i/o ef100 force 100 mbits/ sec. output high rmii only table 3-1. signal description list (continued) signal name function type active level comments
8 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 4. package the AT91SAM7XC512/256/128 is available in 100-lead lqfp green and 100-ball tfbga rohs-compliant packages. 4.1 100-lead lqfp package outline figure 4-1 shows the orientation of the 100-lead lqfp package. a detailed mechanical descrip- tion is given in the mechanical charac teristics section of the full datasheet. figure 4-1. 100-lead lqfp package outline (top view) 125 26 50 51 75 76 100
9 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 4.2 100-lead lqfp pinout table 4-1. pinout in 100-lead lqfp package 1 advref 26 pa18/pgmd6 51 tdi 76 tdo 2 gnd 27 pb9 52 gnd 77 jtagsel 3 ad4 28 pb8 53 pb16 78 tms 4 ad5 29 pb14 54 pb4 79 tck 5 ad6 30 pb13 55 pa23/pgmd11 80 pa30 6 ad7 31 pb6 56 pa24/pgmd12 81 pa0/pgmen0 7 vddout 32 gnd 57 nrst 82 pa1/pgmen1 8 vddin 33 vddio 58 tst 83 gnd 9 pb27/ad0 34 pb5 59 pa25/pgmd13 84 vddio 10 pb28/ad1 35 pb15 60 pa26/pgmd14 85 pa3 11 pb29/ad2 36 pb17 61 vddio 86 pa2 12 pb30/ad3 37 vddcore 62 vddcore 87 vddcore 13 pa8/pgmm0 38 pb7 63 pb18 88 pa4/pgmncmd 14 pa9/pgmm1 39 pb12 64 pb19 89 pa5/pgmrdy 15 vddcore 40 pb0 65 pb20 90 pa6/pgmnoe 16 gnd 41 pb1 66 pb21 91 pa7/pgmnvalid 17 vddio 42 pb2 67 pb22 92 erase 18 pa10/pgmm2 43 pb3 68 gnd 93 ddm 19 pa11/pgmm3 44 pb10 69 pb23 94 ddp 20 pa12/pgmd0 45 pb11 70 pb24 95 vddflash 21 pa13/pgmd1 46 pa19/pgmd7 71 pb25 96 gnd 22 pa14/pgmd2 47 pa20/pgmd8 72 pb26 97 xin/pgmck 23 pa15/pgmd3 48 vddio 73 pa27/pgmd15 98 xout 24 pa16/pgmd4 49 pa21/pgmd9 74 pa28 99 pllrc 25 pa17/pgmd5 50 pa22/pgmd10 75 pa29 100 vddpll
10 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 4.3 100-ball tfbga package outline figure 4-2 shows the orientation of the 100-ball tfbga package. a detailed mechanical description is given in the mechanical characteristics section of the full datasheet. figure 4-2. 100-ball tfbga package orientation (top view) 4.4 100-ball tfbga pinout 1 3 4 5 6 7 8 9 10 2 abcdefghjk top view ball a1 table 4-2. pinout in 100-ball tfbga package pin signal name pin signal name pin signal name pin signal name a1 pa22/pgmd10 c6 pb17 f1 pb21 h6 pa7/pgmnvalid a2 pa21/pgmd9 c7 pb13 f2 pb23 h7 pa9/pgmm1 a3 pa20/pgmd8 c8 pa13/pgmd1 f3 pb25 h8 pa8/pgmm0 a4 pb1 c9 pa12/pgmd0 f4 pb26 h9 pb29/ad2 a5 pb7 c10 pa15/pgmd3 f5 tck h10 pllrc a6 pb5 d1 pa23/pgmd11 f6 pa6/pgmnoe j1 pa29 a7 pb8 d2 pa24/pgmd12 f7 erase j2 pa30 a8 pb9 d3 nrst f8 vddcore j3 pa0/pgmen0 a9 pa18/pgmd6 d4 tst f9 gnd j4 pa1/pgmen1 a10 vddio d5 pb19 f10 vddin j5 vddflash b1 tdi d6 pb6 g1 pb22 j6 gnd b2 pa19/pgmd7 d7 pa10/pgmm2 g2 pb24 j7 xin/pgmck b3 pb11 d8 vddio g3 pa27/pgmd15 j8 xout b4 pb2 d9 pb27/ad0 g4 tdo j9 gnd b5 pb12 d10 pa11/pgmm3 g5 pa2 j10 vddpll b6 pb15 e1 pa25/pgmd13 g6 pa5/pgmrdy k1 vddcore b7 pb14 e2 pa26/pgmd14 g7 vddcore k2 vddcore b8 pa14/pgmd2 e3 pb18 g8 gnd k3 ddp b9 pa16/pgmd4 e4 pb20 g9 pb30/ad3 k4 ddm b10 pa17/pgmd5 e5 tms g10 vddout k5 gnd c1 pb16 e6 gnd h1 vddcore k6 ad7 c2 pb4 e7 vddio h2 pa28 k7 ad6 c3 pb10 e8 pb28/ad1 h3 jtagsel k8 ad5 c4 pb3 e9 vddio h4 pa3 k9 ad4 c5 pb0 e10 gnd h5 pa4/pgmncmd k10 advref
11 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 5. power considerations 5.1 power supplies the AT91SAM7XC512/256/128 has six types of power supply pins and integrates a voltage reg- ulator, allowing the device to be supplied with only one voltage. the six power supply pin types are: vddin pin. it powers the voltage regulator and the adc; voltage ranges from 3.0v to 3.6v, 3.3v nominal. in order to decrease current consumption, if the voltage regulator and the adc are not used, vddin, advref,ad4, ad5, ad6 and ad7 should be connected to gnd. in this case, vddout should be left unconnected. vddout pin. it is the output of the 1.8v voltage regulator. vddio pin. it powers the i/o lines; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddflash pin. it powers the usb transceivers and a part of the flash and is required for the flash to operate correctly; voltage ranges from 3.0v to 3.6v, 3.3v nominal. vddcore pins. they power the logic of the device; voltage ranges from 1.65v to 1.95v, 1.8v typical. it can be connected to the vddout pin with decoupling capacitor. vddcore is required for the device, including its embedded flash, to operate correctly. vddpll pin. it powers the oscillator and the pll. it can be connected directly to the vddout pin. no separate ground pins are provided for the diff erent power supplies. only gnd pins are pro- vided and should be connected as shortl y as possible to the system ground plane. 5.2 power consumption the AT91SAM7XC512/ 256/128 has a static current of less than 60 a on vddcore at 25c, including the rc oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. activating the brownout detector adds 28 a static current. the dynamic power consumption on vddcore is less than 90 ma at full speed when running out of the flash. under the sa me conditions, the power consum ption on vddflash does not exceed 10 ma. 5.3 voltage regulator the AT91SAM7XC512/256/128 embeds a voltage regulator that is managed by the system controller. in normal mode, the voltage regulator consumes less than 100 a static current and draws 100 ma of output current. the voltage regulator also has a low-power mode. in this mode, it consumes less than 25 a static current and draws 1 ma of output current. adequate output supply decoupling is mandator y for vddout to reduce ripple and avoid oscil- lations. the best way to achieve this is to use two capacitors in parallel: one external 470 pf (or 1 nf) npo capacitor should be connected between vddout and gnd as close to the chip as possible. one external 2.2 f (or 3.3 f) x7r capacitor should be connected between vddout and gnd.
12 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary adequate input supply decouplin g is mandatory for vddin in or der to improve startup stability and reduce source voltage drop. the input decoupling capacitor should be placed close to the chip. for example, two capacitors can be used in parallel: 100 nf npo and 4.7 f x7r. 5.4 typical powe ring schematics the AT91SAM7XC512/256/128 supports a 3.3v single supply mode. the internal regulator input connected to the 3.3v source and its output feeds vddcore and the vddpll. figure 5- 1 shows the power schematics to be used for usb bus-powered systems. figure 5-1. 3.3v system single power supply schematic power source ranges from 4.5v (usb) to 18v 3.3v vddin voltage regulator vddout vddio dc/dc converter vddcore vddflash vddpll
13 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 6. i/o lines considerations 6.1 jtag port pins tms, tdi and tck are schmitt trigger inputs and are not 5-v tolerant. tms, tdi and tck do not integrate a pull-up resistor. tdo is an output, driven at up to vddio, and has no pull-up resistor. the jtagsel pin is used to select the jtag boundary scan when asserted at a high level. the jtagsel pin integrates a permanent pull-down resistor of about 15 k #! to gnd, so that it can be left unconnected for normal operations. 6.2 test pin the tst pin is used for manufacturing test or fast programming mode of the AT91SAM7XC512/256/128 when asserted high. the tst pin integrates a permanent pull-down resistor of about 15 k # to gnd, so that it can be left unconnected for normal operations. to enter fast programming mode, the tst pin and the pa0 and pa1 pins should be tied high and pa2 tied to low. driving the tst pin at a high level while pa0 or pa1 is driven at 0 leads to unpredictable results. 6.3 reset pin the nrst pin is bidirectional with an open drain ou tput buffer. it is handled by the on-chip reset controller and can be driven low to provide a rese t signal to the external components or asserted low externally to reset the microcontroller. there is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pu lse length. this allows connection of a sim- ple push-button on the nrst pin as system user reset, and the use of the signal nrst to reset all the components of the system. the nrst pin integrates a permanent pull-up resistor to vddio $ 6.4 erase pin the erase pin is used to re-initialize the flash content and some of its nvm bits. it integrates a permanent pull-down resistor of about 15 k # to gnd, so that it can be left unconnected for nor- mal operations. this pin is debounced by the rc oscillator to improve the glitch tolerance. minimum debouncing time is 200 ms. 6.5 pio controller lines all the i/o lines, pa0 to pa30 and pb0 to pb30, are 5v-tolerant and all integrate a programma- ble pull-up resistor. programming of this pull-up resistor is performed independently for each i/o line through the pio controllers. 5v-tolerant means that the i/o lines can drive voltage level according to vddio, but can be driven with a voltage of up to 5.5v. however, dr iving an i/o line with a voltage over vddio while the programmable pull- up resistor is enabled will create a cu rrent path through the pull-up resis- tor from the i/o line to vddio. care should be taken, in particular at reset, as all the i/o lines default to input with pull-up resistor enabled at reset.
14 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 6.6 i/o lines current drawing the pio lines pa0 to pa3 are high-drive current capable. each of these i/o lines can drive up to 16 ma permanently. the remaining i/o lines can draw only 8 ma. however, the total current drawn by all the i/o lines cannot exceed 200 ma.
15 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 7. processor and architecture 7.1 arm7tdmi processor risc processor based on armv4t von neumann architecture ? runs at up to 55 mhz, providing 0.9 mips/mhz two instruction sets ?arm ? high-performance 32-bit instruction set ?thumb ? high code density 16-bit instruction set three-stage pipeline architecture ? instruction fetch (f) ? instruction decode (d) ? execute (e) 7.2 debug and test features integrated embedded in-circuit emulator ? two watchpoint units ? test access port accessible through a jtag protocol ? debug communication channel debug unit ?two-pin uart ? debug communication channel interrupt handling ? chip id register ieee1149.1 jtag boundary-scan on all digital pins 7.3 memory controller programmable bus arbiter ? handles requests from the arm7tdmi, the ethernet mac and the peripheral dma controller address decoder provides selection signals for ? three internal 1 mbyte memory areas ? one 256 mbyte embedded peripheral area abort status registers ? source, type and all parameters of the access leading to an abort are saved ? facilitates debug by de tection of bad pointers misalignment detector ? alignment checking of all data accesses ? abort generation in case of misalignment remap command ? remaps the sram in place of the embedded non-volatile memory ? allows handling of dynamic exception vectors
16 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary embedded flash controller ? embedded flash interface, up to three programmable wait states ? prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states ? key-protected program, erase and lock/unlock sequencer ? single command for erasing, programming and locking operations ? interrupt generation in case of forbidden operation 7.4 peripheral dma controller handles data transfer between peripherals and memories seventeen channels ? two for each usart ? two for the debug unit ? two for the serial synchronous controller ? two for each serial peripheral interface ? two for the advanced encryption standard 128-bit accelerator ? two for the triple data encryption standard 128-bit accelerator ? one for the analog-to-digital converter low bus arbitration overhead ? one master clock cycle needed for a transfer from memory to peripheral ? two master clock cycles needed for a transfer from peripheral to memory next pointer management for reducing interrupt latency requirements
17 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 8. memory 8.1 AT91SAM7XC512 512 kbytes of dual-plane flash memory ? 2 contiguous banks of 1024 pages of 256 bytes ? fast access time, 30 mhz single-cycle access in worst case conditions ? page programming time: 6 ms, including page auto-erase ? page programming without auto-erase: 3 ms ? full chip erase time: 15 ms ? 10,000 write cycles, 10-yea r data retent ion capability ? 32 lock bits, protecting 32 sectors of 64 pages ? protection mode to secure contents of the flash 128 kbytes of fast sram ? single-cycle access at full speed 8.2 at91sam7xc256 256 kbytes of flash memory ? 1024 pages of 256 bytes ? fast access time, 30 mhz single-cycle access in worst case conditions ? page programming time: 6 ms, including page auto-erase ? page programming without auto-erase: 3 ms ? full chip erase time: 15 ms ? 10,000 write cycles, 10-yea r data retent ion capability ? 16 lock bits, each protecting 16 sectors of 64 pages ? protection mode to secure contents of the flash 64 kbytes of fast sram ? single-cycle access at full speed 8.3 at91sam7xc128 128 kbytes of flash memory ? 512 pages of 256 bytes ? fast access time, 30 mhz single-cycle access in worst case conditions ? page programming time: 6 ms, including page auto-erase ? page programming without auto-erase: 3 ms ? full chip erase time: 15 ms ? 10,000 write cycles, 10-yea r data retent ion capability ? 8 lock bits, each protecting 8 sectors of 64 pages ? protection mode to secure contents of the flash 32 kbytes of fast sram ? single-cycle access at full speed
18 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary figure 8-1. AT91SAM7XC512/256/128 memory mapping 0x1000 0000 0x0000 0000 0x0fff ffff 0xf000 0000 0xefff ffff 0xffff ffff 256 mbytes 256 mbytes 14 x 256 mbytes 3,584 mbytes 0x000f fff 0x0010 0000 0x001f fff 0x0020 0000 0x002f fff 0x0030 0000 0x003f fff 0x0040 0000 0x0000 0000 1 mbytes 1 mbytes 1 mbytes 1 mbytes 252 mbytes 0xfffa 0000 0xfffa bfff 0xfffa c000 0xf000 0000 0xfffb 8000 0xfffc 0000 0xfffc 3fff 0xfffc 4000 0xfffc 7fff 0xfffd 4000 0xfffd 7fff 0xfffd 3fff 0xfffd ffff 0xfffe 0000 0xfffe 3fff 0xffff efff 0xfffe f000 0xffff ffff 0xfffe 4000 0xfffe 8000 0xfffe 7fff 0xfffb 4000 0xfffb 7fff 0xfff9 ffff 0xfffa 3fff 0xfffa 7fff 0xfffc ffff 0xfffd 8000 0xfffd bfff 0xfffc bfff 0xfffc c000 0xfffb ffff 0xfffb c000 0xfffb bfff 0xfffa ffff 0xfffb 0000 0xfffb 3fff 0xfffd 0000 0xfffd c000 0xfffc 8000 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 0xfffa 4000 16 kbytes 0xfffa 0000 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 16 kbytes 0x0fff ffff 512 bytes/128 registers 512 bytes/128 registers 256 bytes/64 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 16 bytes/4 registers 256 bytes/64 registers 4 bytes/1 register 512 bytes/128 registers 512 bytes/128 registers 0xffff f000 0xffff f200 0xffff f1ff 0xffff f3ff 0xffff fbff 0xffff fcff 0xffff feff 0xffff ffff 0xffff f400 0xffff fc00 0xffff fd0f 0xffff fc2f 0xffff fc3f 0xffff fd4f 0xffff fc6f 0xffff f5ff 0xffff f600 0xffff f7ff 0xffff f800 0xffff fd00 0xffff ff00 0xffff fd20 0xffff fd30 0xffff fd40 0xffff fd60 0xffff fd70 internal memories undefined (abort) (1) can be rom, flash or sram depending on gpnvm2 and remap flash before remap sram after remap internal flash internal sram internal rom reserved boot memory (1) address memory space internal memory mapping note: tc0, tc1, tc2 aes 128 tdes usart0 usart1 pwmc reserved reserved reserved reserved reserved reserved reserved reserved can emac reserved twi ssc spi0 spi1 udp adc aic dbgu pioa reserved pmc mc wdt pit rtt rstc vreg piob peripheral mapping system controller mapping internal peripherals reserved sysc
19 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 8.4 memory mapping 8.4.1 internal ram the AT91SAM7XC512 embeds a high-speed 128-kbyte sram bank. the at91sam7xc256 embeds a hi gh-speed 64-kbyte sram bank. the at91sam7xc128 embeds a hi gh-speed 32-kbyte sram bank. after reset and until the remap command is performed, the sram is only accessible at address 0x0020 0000. after remap, the sram also becomes available at address 0x0. 8.4.2 internal rom the AT91SAM7XC512/256/128 embeds an internal rom. at any time, the rom is mapped at address 0x30 0000. the rom contains the ffpi and the sam-ba program. 8.4.3 internal flash the AT91SAM7XC512 features two banks (dual plane) of 256 kbytes of flash. the at91sam7xc256 features one bank (s ingle plane) of 256 kbytes of flash. the at91sam7xc128 features one bank (s ingle plane) of 128 kbytes of flash. at any time, the flash is mapped to address 0x0010 0000. it is also accessible at address 0x0 after the reset, if gpnvm bit 2 is cleared and before the remap command. a general purpose nvm (gpnvm) bit is used to boot either on the rom (default) or from the flash. this gpnvm bit can be cleared or set respecti vely through the commands ?clear general-pur- pose nvm bit? and ?set general-purpose nvm bit? of the efc user interface. setting the gpnvm bit 2 selects the boot from the flash. asserting erase clears the gpnvm bit 2 and thus selects the boot from the rom by default. figure 8-2. internal memory mapping with gpnvm bit 2 = 0 (default) 256m bytes rom before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1 m bytes 1 m bytes 1 m bytes 252 m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 internal rom 0x003f ffff 0x0040 0000 1 m bytes
20 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary figure 8-3. internal memory mapping with gpnvm bit 2 = 1 8.5 embedded flash 8.5.1 flash overview the flash of the AT91SAM7XC512 is organized in two banks (dual plane) 0f 1254 pages of 256 bytes. the 524, 288 bytes are organized in 32-bit words. the flash of the at91sam7xc256 is organized in 1024 pages of 256 bytes (single plane). it reads as 65,536 32-bit words. the flash of the at91sam7xc128 is organized in 512 pages of 256 bytes (single plane). it reads as 32,768 32-bit words. the flash contains a 256-byte write buffer, accessible through a 32-bit interface. the flash benefits from the integration of a power reset cell and from the brownout detector. this prevents code corruption during power su pply changes, even in the worst conditions. when flash is not used (read or write access), it is automatically placed into standby mode. 8.5.2 embedded flash controller the embedded flash controller (efc) manages accesses performed by the masters of the sys- tem. it enables reading the flash and writing the write buffer. it also contains a user interface, mapped within the memory co ntroller on the apb. the user interface allows: programming of the access parameters of the flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, nvm bit set, nvm bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors the embedded flash controller also provides a dual 32-bit prefetch buffer that optimizes 16-bit access to the flash. this is particularly efficient when the processor is running in thumb mode. two efcs are embedded in the AT91SAM7XC512 to control each bank of 256 kbytes. dual- plane organization allows concurrent read and program functionality. read from one memory 256m bytes flash before remap sram after remap undefined areas (abort) 0x000f ffff 0x001f ffff 0x002f ffff 0x0fff ffff 1 m bytes 1 m bytes 1 m bytes 252 m bytes internal flash internal sram 0x0000 0000 0x0010 0000 0x0020 0000 0x0030 0000 internal rom 0x003f ffff 0x0040 0000 1 m bytes
21 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary plane may be performed even while program or er ase functions are being executed in the other memory plane. one efc is embedded in the at91sam7xc256/128 to control the single plane of 256/128 kbytes. 8.5.3 lock regions 8.5.3.1 AT91SAM7XC512 two embedded flash controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. the AT91SAM7XC512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. each lock region has a size of 16 kbytes. if a locked-region?s erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 32 nvm bits are software programmable through both of the efc user interfaces. the com- mand ?set lock bit? enables the protection. the command ?clear lo ck bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 8.5.3.2 at91sam7xc256 the embedded flash controller manages 16 lock bi ts to protect 16 regions of the flash against inadvertent flash erasing or programming commands. the at91sam7xc256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. each lock region has a size of 16 kbytes. if a locked-region?s erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 16 nvm bits are software programmable through the efc user interface. the command ?set lock bit? enables the pr otection. the command ?clear lo ck bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 8.5.3.3 at91sam7xc128 the embedded flash controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. the at91sam7xc128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. each lock region has a size of 16 kbytes. if a locked-region?s erase or program command occurs, the command is aborted and the efc trigs an interrupt. the 8 nvm bits are software programmable through the efc user interface. the command ?set lock bit? enables the protection. the command ?clear lock bit? unlocks the lock region. asserting the erase pin clears the lock bits, thus unlocking the entire flash. 8.5.4 security bit feature the AT91SAM7XC512/256/128 features a security bit, based on a specific nvm-bit. when the security is enabled, any access to the flash, either through the ice interface or through the fast
22 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary flash programming interface, is forbidden. this ensures the confidentiality of the code pro- grammed in the flash. this security bit can only be enabled, through the command ?set security bit? of the efc user interface. disabling the security bit can only be achieved by as serting the erase pin at 1, and after a full flash erase is performed. when the se curity bit is deactivated, all accesses to the flash are permitted. it is important to note that the assertion of the erase pin should always be longer than 220 ms. as the erase pin integrates a permanent pull-down, it can be left unconnected during normal operation. however, it is safer to connect it directly to gnd fo r the final application. 8.5.5 non-volatile brownout detector control two general purpos e nvm (gpnvm) bits are used for c ontrolling the brownout detector (bod), so that even after a power loss, the brownout detector operations remain in their state. these two gpnvm bits can be cleared or set respectively through the commands ?clear gen- eral-purpose nvm bit? and ?set general-pu rpose nvm bit? of the efc user interface. gpnvm bit 0 is used as a brownout detector enable bit. setting the gpnvm bit 0 enables the bod, clearing it disables the bod. asserting erase clears the gpnvm bit 0 and thus disables the brownout detector by default. the gpnvm bit 1 is used as a brownout reset enable signal for the reset controller. setting the gpnvm bit 1 enables the brownout reset when a brownout is detected, clearing the gpnvm bit 1 disables the brownout reset. asserting erase disables the brownout reset by default. 8.5.6 calibration bits eight nvm bits are used to calibrate the brownout detector and the voltage regulator. these bits are factory configured and cannot be changed by the user. the erase pin has no effect on the calibration bits. 8.6 fast flash programming interface the fast flash programming interface allows programming the device through either a serial jtag interface or through a multiplexed fully-han dshaked parallel port. it allows gang-program- ming with market-standard industrial programmers. the ffpi supports read, page program, page erase, full erase, lock, unlock and protect commands. the fast flash programming interface is enabled and the fast programming mode is entered when the tst pin and the pa0 and pa1 pins are all tied high. 8.7 sam-ba boot assistant the sam-ba boot assistant is a default boot program that provides an easy way to program in- situ the on-chip flash memory. the sam-ba boot assistant supports serial co mmunication via the dbgu or the usb device port. communication via the dbgu supports a wide range of crystals from 3 to 20 mhz via software auto-detection.
23 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary communication via the usb device port is limited to an 18.432 mhz crystal. the sam-ba boot provides an interface with sam-ba graphic user interface (gui). the sam-ba boot is in rom and is mapped at address 0x0 when the gpnvm bit 2 is set to 0. when gpnvm bit 2 is set to 1, the device boots from the flash. when gpnvm bit 2 is set to 0, the device boots from rom (sam-ba).
24 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 9. system controller the system controller manages a ll vital blocks of the microcontr oller: interrupts , clocks, power, time, debug and reset. the system controller peripherals are all mapped to the highest 4 kbytes of address space, between addresses 0xffff f000 and 0xffff ffff. figure 9-1 on page 25 shows the system controller block diagram. figure 8-1 on page 18 shows the mapping of the user interface of the system controller periph- erals. note that the memory controller configuration user interface is also mapped within this address space.
25 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary figure 9-1. system controller block diagram nrst slck advanced interrupt controller real-time timer periodic interval timer reset controller pa0-pa30 periph_nreset system controller watchdog timer wdt_fault wdrproc pio controller por bod rcosc gpnvm[0] cal en power management controller osc pll xin xout pllrc mainck pllck pit_irq mck proc_nreset wdt_irq periph_irq{2-3] periph_nreset periph_clk[2..18] pck mck pmc_irq udpck nirq nfiq rtt_irq embedded peripherals periph_clk[2-3] pck[0-3] in out enable arm7tdmi slck slck irq0-irq1 fiq irq0-irq1 fiq periph_irq[4..19] periph_irq[2..19] int int periph_nreset periph_clk[4..19] embedded flash flash_poe jtag_nreset flash_poe gpnvm[0..2] flash_wrdis flash_wrdis proc_nreset periph_nreset dbgu_txd dbgu_rxd pit_irq rtt_irq dbgu_irq pmc_irq rstc_irq wdt_irq rstc_irq efc_irq slck gpnvm[1] boundary scan tap controller jtag_nreset power_on_reset debug pck debug idle debug memory controller mck proc_nreset bod_rst_en proc_nreset periph_nreset periph_nreset idle debug unit dbgu_irq mck dbgu_rxd periph_nreset force_ntrst dbgu_txd usb device port udpck periph_nreset periph_clk[11] periph_irq[11] usb_suspend usb_suspend voltage regulator standby voltage regulator mode controller security_bit cal power_on_reset force_ntrst cal pb0-pb30 efc_irq
26 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 9.1 reset controller based on one power-on reset cell and one brownout detector status of the last reset, either power-up reset, software reset, user reset, watchdog reset, brownout reset controls the internal resets and the nrst pin output allows to shape a signal on the nrst line, guaranteeing that the length of the pulse meets any requirement. 9.1.1 brownout detector and power-on reset the AT91SAM7XC512/256/128 embeds one brownout detection circuit and a power-on reset cell. the power-on reset is supp lied with and monitors vddcore. both signals are provided to the flash to prev ent any code corruption during power-up or power- down sequences or if brownouts occur on the power supplies. the power-on reset cell has a limited-accuracy threshold at around 1.5v. its output remains low during power-up until vddcore go es over this voltag e level. this signal goes to the reset con- troller and allows a full re-initialization of the device. the brownout detector monitors the vddcor e and vddflash levels during operation by comparing them to a fixed trigger level. it secures system operations in the most difficult environ- ments and prevents code corruption in case of brownout on the vddcore or vddflash. when the brownout detector is enabled and vddcor e decreases to a value below the trigger level (vbot18-, defined as vbot18 - hyst/2), the brownout output is immediately activated. when vddcore increases above the trigger leve l (vbot18+, defined as v bot18 + hyst/2), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the vddcore threshold voltage ha s a hysteresis of about 50 mv , to ensure spike free brown- out detection. the typical value of the brownout detector threshold is 1.68v with an accuracy of 2% and is factory calibrated. when the brownout detector is enabled and vddflash decreases to a value below the trigger level (vbot33-, defined as vbot33 - hyst/2), the brownout output is immediately activated. when vddflash increases above the trigger level (vbot33+, defined as vbot33 + hyst/2), the reset is released. the brownout detector only detects a drop if the voltage on vddcore stays below the threshold voltage for longer than about 1s. the vddflash threshold voltage has a hysteresis of about 50 mv, to ensure spike free brown- out detection. the typical value of the brownout detector threshold is 2.80v with an accuracy of 3.5% and is factory calibrated. the brownout detector is low-power, as it consum es less than 28 a static current. however, it can be deactivated to save its static current. in this case, it consumes less than 1a. the deac- tivation is configured through the gpnvm bit 0 of the flash.
27 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 9.2 clock generator the clock generator embeds one low-power rc oscillator, one main oscillator and one pll with the following characteristics: rc oscillator ranges betw een 22 khz and 42 khz main oscillator frequency ranges between 3 and 20 mhz main oscillator can be bypassed pll output ranges between 80 and 200 mhz it provides slck, mainck and pllck. figure 9-2. clock generator block diagram embedded rc oscillator main oscillator pll and divider clock generator power management controller xin xout pllrc slow clock slck main clock mainck pll clock pllck control status
28 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 9.3 power management controller the power management controller uses the clock generator outputs to provide: the processor clock pck the master clock mck the usb clock udpck all the peripheral clocks, independently controllable four programmable clock outputs the master clock (mck) is programmable from a few hundred hz to the maximum operating fre- quency of the device. the processor clock (pck) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. figure 9-3. power management co ntroller block diagram 9.4 advanced interrupt controller controls the interrupt lines (nirq and nfiq) of an arm processor individually maskable and vectored interrupt sources ? source 0 is reserved for the fast interrupt input (fiq) ? source 1 is reserved for system peripherals (rtt, pit, efc, pmc, dbgu, etc.) ? other sources control the peripheral interrupts or external interrupts ? programmable edge-triggered or level-sensitive internal sources ? programmable positive/negative edge-triggered or high/low level-sensitive external sources 8-level priority controller ? drives the normal interrupt nirq of the processor ? handles priority of the interrupt sources mck periph_clk[2..18] int udpck slck mainck pllck prescaler /1,/2,/4,...,/64 pck processor clock controller idle mode master clock controller peripherals clock controller on/off usb clock controller on/off slck mainck pllck prescaler /1,/2,/4,...,/64 programmable clock controller pllck divider /1,/2,/4 pck[0..3]
29 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary ? higher priority interrupts can be served during service of lower priority interrupt vectoring ? optimizes interrupt service routine branch and execution ? one 32-bit vector register per interrupt source ? interrupt vector register reads the corresponding current interrupt vector protect mode ? easy debugging by preventing automatic operations fast forcing ? permits redirecting any interrupt source on the fast interrupt general interrupt mask ? provides processor synchronization on events without triggering an interrupt 9.5 debug unit comprises: ? one two-pin uart ? one interface for the debug co mmunication channel (dcc) support ? one set of chip id registers ? one interface providing ice access prevention two-pin uart ? usart-compatible user interface ? programmable baud rate generator ? parity, framing and overrun error ? automatic echo, local loopback and remote loopback channel modes debug communication channel support ? offers visibility of commrx and commt x signals from the arm processor chip id registers ? identification of the device revision, sizes of the embedded memories, set of peripherals ? chip id is 0x271c 0a40 (version 0) for AT91SAM7XC512 ? chip id is 0x271b 0940 (version 0) for at91sam7xc256 ? chip id is 0x271a 0740 (version 0) for at91sam7xc128 9.6 periodic interval timer 20-bit programmable counter plus 12-bit interval counter 9.7 watchdog timer 12-bit key-protected programmable counter running on prescaled slck provides reset or interrupt signals to the system counter may be stopped while the processor is in debug state or in idle mode 9.8 real-time timer 32-bit free-running counter with alarm running on prescaled slck
30 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary programmable 16-bit prescaler for slck accuracy compensation 9.9 pio controllers two pio controllers, each controlling 31 i/o lines fully programmable through set/clear registers multiplexing of two peripheral functions per i/o line for each i/o line (whether assigned to a peripheral or used as general-purpose i/o) ? input change interrupt ? half a clock period glitch filter ? multi-drive option enables driving in open drain ? programmable pull-up on each i/o line ? pin data status register, supplies visib ility of the level on the pin at any time synchronous output, provides set and clear of several i/o lines in a single write 9.10 voltage regulator controller the purpose of this controller is to select the power mode of the voltage regulator between normal mode (bit 0 is cleared) or standby mode (bit 0 is set).
31 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 10. peripherals 10.1 user interface the user peripherals are mapped in the 256 mbytes of address space between 0xf000 0000 and 0xfffe ffff. each peripheral is allocated 16 kbytes of address space. a complete memory map is provided in figure 8-1 on page 18 . 10.2 peripheral identifiers the AT91SAM7XC512/256/128 embeds a wide range of peripherals. table 10-1 defines the peripheral identifiers of the AT91SAM7XC512/256/128. unique peripheral identifiers are defined for both the advanced interrupt controller and the power management controller. note: 1. setting sysc and adc bits in the clock set/clear re gisters of the pmc has no effect. the sys- tem controller and adc are continuously clocked. table 10-1. peripheral identifiers peripheral id peripheral mnemonic peripheral name external interrupt 0 aic advanced interrupt controller fiq 1 sysc (1) system 2 pioa parallel i/o controller a 3 piob parallel i/o controller b 4 spi0 serial peripheral interface 0 5 spi1 serial peripheral interface 1 6 us0 usart 0 7 us1 usart 1 8 ssc synchronous serial controller 9 twi two-wire interface 10 pwmc pulse width modulation controller 11 udp usb device port 12 tc0 timer/counter 0 13 tc1 timer/counter 1 14 tc2 timer/counter 2 15 can can controller 16 emac ethernet mac 17 adc (1) analog-to digital converter 18 aes advanced encryption standard 128-bit 19 tdes triple data encryption standard 20-29 reserved 30 aic advanced interrupt controller irq0 31 aic advanced interrupt controller irq1
32 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 10.3 peripheral multiplexing on pio lines the AT91SAM7XC512/256/128 features two pio controllers, pioa and piob, that multiplex the i/o lines of the peripheral set. each pio controller controls 31 lines. each line can be assigned to one of two peripheral func- tions, a or b. some of them can also be multiplexed with the analog inputs of the adc controller. table 10-2 on page 33 and table 10-3 on page 34 defines how the i/o lines of the peripherals a, b or the analog inputs are multiplexed on the pio controller a and pio controller b. the two columns ?function? and ?comments? have been inserted for the user?s own comments; they may be used to track how pins are defined in an application. note that some peripheral functions that are output only, may be duplicated in the table. at reset, all i/o lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.
33 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 10.4 pio controller a multiplexing table 10-2. multiplexing on pio controller a pio controller a application usage i/o line peripheral a peripheral b comments function comments pa0 rxd0 high-drive pa1 txd0 high-drive pa2 sck0 spi1_npcs1 high-drive pa3 rts0 spi1_npcs2 high-drive pa4 cts0 spi1_npcs3 pa 5 r x d 1 pa 6 t x d 1 pa7 sck1 spi0_npcs1 pa8 rts1 spi0_npcs2 pa9 cts1 spi0_npcs3 pa 1 0 t w d pa 1 1 t w c k pa12 spi_npcs0 pa13 spi0_npcs1 pck1 pa14 spi0_npcs2 irq1 pa15 spi0_npcs3 tclk2 pa16 spi0_miso pa17 spi0_mosi pa18 spi0_spck pa19 canrx pa20 cantx pa21 tf spi1_npcs0 pa22 tk spi1_spck pa23 td spi1_mosi pa24 rd spi1_miso pa25 rk spi1_npcs1 pa26 rf spi1_npcs2 pa27 drxd pck3 pa 2 8 d t x d pa29 fiq spi1_npcs3 pa 3 0 irq0 pck2
34 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 10.5 pio controller b multiplexing table 10-3. multiplexing on pio controller b pio controller b application usage i/o line peripheral a peripheral b comments function comments pb0 etxck/erefck pck0 pb1 etxen pb2 etx0 pb3 etx1 pb4 ecrs pb5 erx0 pb6 erx1 pb7 erxer pb8 emdc pb9 emdio pb10 etx2 spi1_npcs1 pb11 etx3 spi1_npcs2 pb12 etxer tclk0 pb13 erx2 spi0_npcs1 pb14 erx3 spi0_npcs2 pb15 erxdv/ecrsdv pb16 ecol spi1_npcs3 pb17 erxck spi0_npcs3 pb18 ef100 adtrg pb19 pwm0 tclk1 pb20 pwm1 pck0 pb21 pwm2 pck1 pb22 pwm3 pck2 pb23 tioa0 dcd1 pb24 tiob0 dsr1 pb25 tioa1 dtr1 pb26 tiob1 ri1 pb27 tioa2 pwm0 ad0 pb28 tiob2 pwm1 ad1 pb29 pck1 pwm2 ad2 pb30 pck2 pwm3 ad3
35 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 10.6 ethernet mac dma master on receive and transmit channels compatible with ieee standard 802.3 10 and 100 mbit/s operation full- and half-duplex operation statistics counter registers mii/rmii interface to the physical layer interrupt generation to signal receive and transmit completion 28-byte transmit fifo and 28-byte receive fifo automatic pad and crc generation on transmitted frames automatic discard of frames received with errors address checking logic supports up to four specific 48-bit addresses support promiscuous mode where all valid received frames are copied to memory hash matching of unicast an d multicast destination addresses physical layer management through mdio interface half-duplex flow control by forc ing collisions on incoming frames full-duplex flow control with recognition of incoming pause frames support for 802.1q vlan tagging with recognition of incoming vlan and priority tagged frames multiple buffers per receive and transmit frame jumbo frames up to 10240 bytes supported 10.7 serial peripheral interface supports communication with external serial devices ? four chip selects with external decoder allow communication with up to 15 peripherals ? serial memories, such as dataflash ? and 3-wire eeproms ? serial peripherals, such as adcs, dacs, lcd controllers, can controllers and sensors ? external co-processors master or slave serial peripheral bus interface ? 8- to 16-bit programmable data length per chip select ? programmable phase and polarity per chip select ? programmable transfer delays per chip select, between consecutive transfers and between clock and data ? programmable delay between consecutive transfers ? selectable mode fault detection ? maximum frequency at up to master clock 10.8 two-wire interface master mode only compatibility with standard two-wire serial memories
36 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary one, two or three bytes for slave address sequential read/write operations 10.9 usart programmable baud rate generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications ? 1, 1.5 or 2 stop bits in asynchronous mode ? 1 or 2 stop bits in synchronous mode ? parity generation and error detection ? framing error detection, overrun error detection ? msb or lsb first ? optional break generation and detection ? by 8 or by 16 over-sampling receiver frequency ? hardware handshaking rts - cts ? modem signals management dtr-dsr-dcd-ri on usart1 ? receiver time-out and transmitter timeguard ? multi-drop mode with address generation and detection rs485 with driver control signal iso7816, t = 0 or t = 1 protocols for interfacing with smart cards ? nack handling, error counter with repetition and iteration limit irda modulation and demodulation ? communication at up to 115.2 kbps test modes ? remote loopback, local loopback, automatic echo 10.10 serial synchronous controller provides serial synchronous communication links used in audio and telecom applications contains an independent receiver and transmitter and a common clock divider offers a configurable frame sync and data length receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal receiver and transmitter include a data signal , a clock signal and a frame synchronization signal 10.11 timer counter three 16-bit timer counter channels ? three output compare or two input capture wide range of functions including: ? frequency measurement ? event counting ? interval measurement ? pulse generation
37 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary ? delay timing ? pulse width modulation ? up/down capabilities each channel is user-configurable and contains: ? three external clock inputs five internal clock inputs, as defined in table 10-4 ? two multi-purpose input/output signals ? two global registers that act on all three tc channels 10.12 pulse width modulation controller four channels, one 16-bit counter per channel common clock generator, providing thirteen different clocks ? one modulo n counter providing eleven clocks ? two independent linear dividers working on modulo n counter outputs independent channel programming ? independent enable/disable commands ? independent clock selection ? independent period and duty cycle, with double buffering ? programmable selection of the output waveform polarity ? programmable center or left aligned output waveform 10.13 usb device port usb v2.0 full-speed compliant,12 mbits per second embedded usb v2.0 full-speed transceiver embedded 1352-byte dual-port ram for endpoints six endpoints ? endpoint 0: 8 bytes ? endpoint 1 and 2: 64 bytes ping-pong ? endpoint 3: 64 bytes ? endpoint 4 and 5: 256 bytes ping-pong ? ping-pong mode (two memory banks) for bulk endpoints suspend/resume logic table 10-4. timer counter clocks assignment tc clock input clock timer_clock1 mck/2 timer_clock2 mck/8 timer_clock3 mck/32 timer_clock4 mck/128 timer_clock5 mck/1024
38 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 10.14 can controller fully compliant with can 2.0a and 2.0b bit rates up to 1mbit/s eight object oriented mailboxes each with the following properties: ? can specification 2.0 part a or 2.0 part b programmable for each message ? object configurable to receive (with overwrite or not) or transmit ? local tag and mask filters up to 29-bit identifier/channel ? 32-bit access to data register s for each mailbox data object ? uses a 16-bit time stamp on receive and transmit message ? hardware concatenation of id unmasked bitfields to speedup family id processing ? 16-bit internal timer for time stamping and network synchronization ? programmable reception buffer length up to 8 mailbox objects ? priority management between transmission mailboxes ? autobaud and listening mode ? low power mode and programmable wake-up on bus activity or by the application ? data, remote, error and overload frame handling 10.15 128-bit advanced e ncryption standard compliant with fips publication 197, advanced encryption standard (aes) 128-bit (at91sam7xc256/128) or 128-bit/192-bit/256-bit (AT91SAM7XC512) cryptographic key 12-clock cycles encryption/decryption processing time (at91sam7xc256/128) 12/13/14-clock cycles encryption/decryption processing time (AT91SAM7XC512) support of the five standard modes of operation specified in the nist special publication 800-38a: ? electronic codebook (ecb) ? cipher block chaining (cbc) ? cipher feedback (cfb) ? output feedback (ofb) ? counter (ctr) 8-, 16-, 32-, 64- and 128-bit data sizes possible in cfb mode last output data mode allowing message authentication code (mac) generation hardware countermeasures against differential power analysis attacks connection to pdc channel capa bilities optimizes data transf ers for all operating modes: ? one channel for the receiver, one channel for the transmitter ? next buffer support 10.16 triple data encryption standard single data encryption standard (des) and triple data encryption algorithm (tdea or tdes) supports compliant with fips publication 46-3 , data encryption standard (des)
39 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 64-bit cryptographic key two-key or three-key algorithms 18-clock cycles encryption/decryption processing time for des 50-clock cycles encryption/decryption processing time for tdes support the four standard modes of operation specified in the fips publication 81, des modes of operation: ? electronic codebook (ecb) ? cipher block chaining (cbc) ? cipher feedback (cfb) ? output feedback (ofb) 8-, 16-, 32- and 64- data sizes possible in cfb mode last output data mode allowing optimized message (data) authentication code (mac) generation connection to pdc channel capa bilities optimizes data transf ers for all operating modes: ? one channel for the receiver, one channel for the transmitter ? next buffer support 10.17 analog-to-digital converter 8-channel adc 10-bit 384 ksamples/sec. successi ve approximation register adc -3/+3 lsb integral non linearity, -2/+2 lsb differential non linearity integrated 8-to-1 multiplexer, offering eight independent 3.3v analog inputs external voltage reference for better accuracy on low voltage inputs individual enable and disable of each channel multiple trigger sources ? hardware or software trigger ? external trigger pin ? timer counter 0 to 2 outputs tioa0 to tioa2 trigger sleep mode and conversion sequencer ? automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels four of eight analog inputs shared with digital signals
40 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 11. package drawings figure 11-1. lqfp package drawing
41 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary table 11-1. 100-lead lqfp package dimensions symbol millimeter inch min nom max min nom max a 1.60 0.63 a1 0.05 0.15 0.002 0.006 a2 1.35 1.40 1.45 0.053 0.055 0.057 d 16.00 bsc 0.630 bsc d1 14.00 bsc 0.551 bsc e 16.00 bsc 0.630 bsc e1 14.00 bsc 0.551 bsc r2 0.08 0.20 0.003 0.008 r1 0.08 0.003 q0 " 3.5 " 7 " 0 " 3.5 " 7 " % 10 " 0 " % 211 " 12 " 13 " 11 " 12 " 13 " % 311 " 12 " 13 " 11 " 12 " 13 " c 0.09 0.20 0.004 0.008 l 0.45 0.60 0.75 0.018 0.024 0.030 l1 1.00 ref 0.039 ref s 0.20 0.008 b 0.17 0.20 0.27 0.007 0.008 0.011 e 0.50 bsc 0.020 bsc d2 12.00 0.472 e2 12.00 0.472 tolerances of form and position aaa 0.20 0.008 bbb 0.20 0.008 ccc 0.08 0.003 ddd 0.08 0.003
42 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary figure 11-2. 100-tfbga package drawing all dimensions are in mm
43 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary 12. AT91SAM7XC512/256/128 ordering information 13. export regulations statement these commodities, technology or software will be exported from france and the applicable export administration regulations will apply. french, unit ed states and other relevant laws, reg- ulations and requirements regarding the export of products may restrict sale, export and re- export of these products; please assure you cond uct your activities in accordance with the appli- cable relevant export regulations. table 12-1. ordering information ordering code package package type temperature operating range AT91SAM7XC512-au AT91SAM7XC512-cu lqfp 100 tfbga 100 green industrial (-40 " c to 85 " c) at91sam7xc256-au at91sam7xc256-cu lqfp 100 tfbga 100 green industrial (-40 " c to 85 " c) at91sam7xc128-au at91sam7xc128-cu lqfp 100 tfbga 100 green industrial (-40 " c to 85 " c)
44 6209bs?atarm?03-sep-06 at91sam7xc/512/256/128 preliminary summary revision history table 13-1. revision history doc. rev comments change request ref. 6209s first issue - unqualified on intranet legal page updated.qualified on intranet 6209bs added AT91SAM7XC512 to product family. ?features? on page 1 and global reformatted memories section 8. ?memory? on page 17 . reordered sub sections in peripherals section 10. ?peripherals? on page 31 consolidated memory mapping in figure 8-1 on page 18 . added package drawings section 11. ?package drawings? on page 40 . consolidated memory mapping in figure 8-1 on page 18 . added tfbga information section 4.3 ?100-ball tfbga package outline? on page 10 . and section 4.4 on page 10 and ?features? on page 1 added lqfp and tfbga package drawings section 11. on page 40 . system controller block diagram figure 9-1 on page 25 , ?ice_nreset? signals changed to ?power_on_reset?. 2729
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